Texas Avenger "TA" Driver series - Triple channel + Bistro or Narsil + Clicky or E-switch - The Ultimate open source driver!

Sorry, still don't understand. Can you tell me what voltage/connection is on the GRND pin #4, and what is going to the VCC pin #8? The difference needs to be 1S, and I dunno what is going into VCC compared to GRND. That's all that matters to run the MCU properly.

Also I don't understand in a 4S configuration how you could possibly get one of those cells to peal off just it's 1S voltage?

From the pics above, I can't see any connection between those 4 pads on the bottom side of the driver? Are they supposed to be connected to complete the 4S configuration?

Sorry - this is why I didn't look into this much -- I just don't get it - something basic I'm not understanding I guess...

Hhmmm, Think'n in a 4S configuration for example, you could peel off the 3S output of Batt+ for your GRND, then the 4S total output would be your VCC? Is that what you are doing? Because then, the difference is a true 1S - doesn't have to be negaitve, just the difference between 3S and 4S can run the MCU?

Yes, like it says on the silk screen you need to bridge the pads according to the cell setup you want, 2s, or 4s.

The voltage the MCU sees is 4.2v across VCC to ground. It is connected to only 1 cell.

This is possible because with a 4s setup all the power runs through the cells and never needs to enter the body of the flashlight (part of why big manufacturers prefer series setups). So since the body of the flashlight would not be connected to ground I am simply using that as a free contact point to the tail of the light.

By connecting the 1st cell in the series ground to the flashlight body the body of the light sees 4.2v to V+ (the TA pad).

The only thing that sees the 4s voltage is the ground pad (with the line of vias).

So basically it is a normal SRK setup far as the MCU is concerned, the positive is on bottom of the driver and the ground comes through the flashlight body.

The FET on the other hand sees the end of the cell series ground, so it has a full 16.8V if you check it to V+.

It is just like a series cell pack from a laptop or anything else. You can take a voltage reading across the whole pack or you can read each cell individually. This is the same way that balance chargers work.

Kinda, it is hard to explain and understand this in words lol. It sounds like you are saying the opposite of what I am doing basically.

I use the cell that connects the positive to the TA pad as the one to power the MCU AND LED as it is better to have ground running through the light then positive. So the other side of that cell (which is ground) connects to the body of the light AND to the rest of the 4s series. The body ground then connects to the MCU to give it a 1s voltage across it.

The other 3 cells keep going in series like normal and ground to the pad with the line of vias which connect ONLY to the FET and 7135. Thus giving them a full 4s voltage across them to positive.

So I am really peeling off 1s and letting the other 3s go to the LED.

So, if I understand this for a 4S setup, 3S is going into GRND and 4S is going into VCC? The 3S is from the ground ring, and 4S is on the TA pad. That should work. Is this correct?

1S is the potential difference. I think if you take 4 cells in series, connect/measure between the 1st cell and 2nd, (1st cell has the batt+ exposed), you are actually at 3S+, not 1S negative.

Oopsie - we keep crossing posts, me, with my editing...

Chuckle, chuckle… I’m with ya tom, this is hard to see. TA, what about a diagram?

I started to do that but could not figure out how to explain it, I will give it another go, be it a bit crude.

Maybe a picture would help? This is how I understand it, I don’t know why it wouldn’t work, though I am still skeptical for some reason. (and technically this isn’t totally correct, obviously the LEDs go through the FET to get to the Batt-, but by “Driver” I mean “MCU”)

Yep, that is it, Same thing I just made up lol:

To me, this is much clearer, but I understood it in the last post this way before the pic - sorry.

Now, isn't this 3S+ for GRND, 4S+ for VCC? So 3S+ is going through the body?

Btw, that pic is exactly what I pictured in my head, finally... My head is a bit thick today, so tuff to get thru.

1s is going through the body to the ground ring on the driver. The other 3s is going to the contact pad on the driver that feeds the FET (the one with the line of vias).

You are talking abut a 4S setup? So in the pictures, isn't 4S going to feed the FET?

Correct, you kept talking about 1s and 3s so I was trying to use your terms to explain it.

LED = 4s

MCU = 1s

All I'm saying is 16V - 12V is 4V, so that's what the MCU is seeing - tapping in between the 3rd and 4th cell (going from negative to positive) gives you 12V. The + end of the 4th cell is 16V. I can't see it any other way from the pics in posts 259 and 260. So in relation to earth ground, 12V would be going through the body, I would think?

In a 2S2P, only 4V would be going through the body?

I think some of the confusion is about the order of the cells. I am calling the 1st cell the one on the far left of my diagram.

The body of the light carries 4.2v through it, just like a normal SRK as that single cell is all that is passing through the body.

The other 3 cells only connect to the contact plate in the tail and to the driver contact pads, which feeds into the FET on cell # 4 (the one on the far right).

I discussed this with an EE friend here @work. His concern was the gate voltage compared to the source voltage coming to the FET. He reviewed the specs on the SIR800DP: N-channel, Vgs rated at +/- 12V.

Have you tried this on the bench yet? Were you planning on using one of our standard FET's? Have you looked into the voltage delta between the gate and source of the FET?

No, I have not done anything more than the design in the OP, just a proof of concept really.

I was not real worried about the FET as I know they exist that would work. For example the old classic NXP have a gate to source voltage of 20v.

http://www.nxp.com/documents/data_sheet/PSMN3R0-30YLD.pdf

I am sure there are more options as well but the NXP is already proven and would work fine. I honestly notice very little difference in the real world between it and the sir800.

For the NXP, yes, it won't blow up anything with a range of 20V, but the source to the FET is -12V compared to the MCU's supplied gate voltage to the FET, so even for the NXP, the FET will be always be on. This is what my friend is saying.

I am not an expert on FET’s by any means.

When the MCU is not sending any voltage to the FET gate, It is an open circuit correct? I am not sure how the FET would turn on with an open circuit on the gate?

When the MCU sends the voltage output to the FET would it not turn on anyways?

Honestly I am not seeing how this setup is any different than using an LDO? Either way the gate sees +4v and the source is –12v?

I guess it is my turn to miss something?

The source is -12V, while the gate is 0 to 4V, therefore when the MCU outputs what it thinks is zero, the FET sees it as +12V, because to the FET, the -12V is it's ground. So when you think you set the gate to 0, it's really a 12V difference over the source input to the FET, so, the FET is always on.

That's the way I understand it. Think it makes sense.

Yes, it makes sense on one hand, IF the circuit was set to 0v by the MCU. The way I understand it though is that when the MCU turns the FET off the circuit is open with no connection at all. Thus how does the FET get energized if there is not a complete circuit?

Even in a zener modded 2s setup there is a 4.1v difference between the source and the gate, this is more than enough to energize the FET if what you are saying is true. Yet zener modded driver work fine?