First a minor thing: I have actually polished off some thoughts on Iadj, but no time to write it up. Basically the diode bias current is going to cause a voltage offset at high resistances, preventing to reach zero, but you get ripple using low resistances. None of it is terrible, but may we may need to live with some compromise between the two. It's mostly unrelated to the two resistor issue.
Now the bad news. For the first time I looked closer at the mosfet. That mosfet has 625nC of gate charge at 10V. I hadn't really noticed that before. That seemed a bit giant to me, and well, it kind of is. That's 63nf of gate capacitance!
Both the potential and charging energy is lost every cycle so just P=CV^2*f (no 1/2). Switching voltage is 6V, fixed in the IC (Vin-Vcc).
so 63E-9*6^2*1E6 = 2.268 W! (I hope I made a mistake here, but I don't think so)
That doesn't sound sooo aweful, but that's happening all the time. So at 2W power output, you've got 2.3W of switching loss. No fancy coff correction helps this. Coff, and frequency only are impacted by voltages (and are under our control anyway). This may finally be the reason PWM from full power doesn't work out so bad after all!
There are other mosfet losses that I've barely thought about. It seems very complicated actually and I likely won't ever find time or energy to deal with it all, but anyway this gives us a measure of at least part of it, and some relevant spec to improve.
I'll present the case about Coff when I get time to present it, but it's a triviality compared to this I think. Although the two will be very linked. This may drive the need to care more about how set the frequency.
Time to look carefully at what fets are available again. I read a doc, maybe Ti, exactly warning against overspecced large, low rdson fets, for this reason. We might need to look for something a little less beefy. However, I still probably don't much free time for a bit.