*BLF LT1 Lantern Project) (updated Nov,17,2020)

Off to drill out some orifices on the ’ole 2-mantel Coleman… :wink:

Put me on the list if I am not already

Look’n good.

Yes practical illumination with efficient run time for this lantern please.

Max brightness lumen monsters can be trouble… I actually got chided by a camper once, they complained that my lantern was too bright for them in the next campsite like 75-100 feet away. :blush:

(Which is also why I seconded the adjustable shield request.)

Sorry I missed that development. Previously the driver was a 7135 based design AFAIK.

It’s good to see another controllable linear driver developed from discrete components, instead of just slapping down a bunch of AMCs and PWMing them.

How well does it behave ? e.g. dynamic range, moonlight or firefly ability, etc.

A schematic diagram would be of interest, but if that’s giving away a proprietary design, at least a functional block diagram.

From that layout you posted, my initial reaction for Lexel is that there are far too many, and too fine, thermal vias. surrounding the FET, and the USB charge regulator. As well as being costly to produce (drill wear and time) perforating the pcb like a sieve is counter-productive and mechanically weakening. If taken to the extreme, as here, you end up with more air than copper, and I predict one small bump would be enough to fracture the PCB, given that it has to support the full mass of the cells.

Also not happy about relying on the solder resist to insulate the brass ring from the ground plane beneath it at the top, once soldered on. It might work if you specified the solder resist to tent the vias, but it’s not good practice, given the possibility of a hard short to the battery, and most good PCB manufacturers will not tent vias, for legitimate reliability concerns.

Edit: PS: there are also vias in the pads of e.g. C7 and C11, and nearly one in R18, which is usually a no-no. Particularly in this case, when if solder enters the via it will increase the chance of it penetrating to the brass ring when it is fitted.

From my experience top part defenitly not have enough surface area for 10w now.

Lamp may be used also indoor. So it should work normally at least at 30C and no moving air. I don’t want to check every 30 if is right temperature.

It is stupid not to use bottom part for cooling if it is possible. It allows to decrease overall mass and use thermal control.

It is stupid if that is easy to design into the lantern and does not add cost, but I would not call it stupid if it does complicate the design and costs and if tests prove that it is not needed for function.

I’ll take one

No :cry:
That is a picture of the PCB design

Brass ring in latest version has also silk to cover the viases, practically the 0.3mm and 0.35mm viases will be for sure covered with 2 layers ink, there is no solder paste on the area so no risk if the bosrds have not huge silk and mask defects
We can always let in production also let them use Kapton tape for more security than that

Dynamic range with PWMing the FET OPAmps will be higher than with AMCs

Who cares if the fab has increased drill work
Even if it looks like swiss cheese those viases conduct heat much better than a simple copper plane on both sides, you see it a lot on boards with thermal load on it

I have let made MF03 board with this via density and it works, a test with MF02 with 0.3mm viases and less space between then did not fully cover with copper as it was more than 1000 per square inch, also 0.35mm viases work a lot better

also MCU with 14 pin might be an option to get all done

As I said simple copper tube around central bolt could be used as heat pipe.

Of course we can wait tests and think about this after.

@Lexel
Is the one pad not to near on the shelf for the driver?
Die Q8 hat eine geschwungene Ausformung, ca. wie die blaue Linie

We do if we have to pay for it. This is Budget Light Forum :wink: Granted, I don’t know much about PCB manufacturing but that drilling certainly looks like it will add something to fabrication time. And I’m pretty sure time is money, even in China. But given how they work, if it’s a problem, they’ll just quietly remove them lol Something to watch out for.

Anyway, if it’s needed to handle the thermal load on the FETs then it’s needed. Never had any problems running FETs in linear mode myself but better safe than sorry.

You pay for area and extra services,
For example ten 10x10cm tray with 4 separate boards
4.99$ Even with 1000 drill holes

The extra services get pricey
Gold plating chemical ENIG 12$
Hatd gold 100$
Purple color 22$
4 layer 40$
0.2mm min. drill size 30$
0.1mm solder stop mask 50$
Blind/buried viases 200$
And so on

When procuring PCBs in commercial quantities the traces come for free, as long as they are within design rules.

The most costly thing about them is the number and different sizes of the drilled holes, each of which has to be done individually by the CNC machine, the maximum stack of boards, the pannelisation etc. all affect this.

This is the dominating factor when getting quotations for production (no, not small quantities of prototypes, where the setup costs dominate and details like number and different sizes of holes are less relevant and usually just ignored).

The smaller the diameter of the holes, the more costly. Those carbide drills don’t sharpen themselves

Specify thousands of 0.3mm vias, and prepare to be laughed at by production engineers.

Specify more different size holes than the machine has toolholders for, and again, prepare to be mocked.

I say again, each of these holes has to be drilled individually, one at a time, using an expensive carbide drill which might not even last one pass of a stacked panel, and if it breaks badly can potentially write-off the entire job.

And the way you have placed them, you might as well write “tear along the dotted line” on the silkscreen.

It seems to me that there has been a bit too much negativity in this thread, so I wanna say that I think this project looks incredible, and thank you to all those involved in making it a reality. Your work is very appreciated.

And it’s been said before, but to those dissatisfied with the current direction, we all look forward to seeing your alternative design.

:+1:

AWESOME!

Will the battery shelf measurements big enough for protected cells up to length 69.5 mm / diameter: 18.9 mm ?
https://enerprof.de/shop/batteries/enerpower-battery-3-6v-3500mah-button-top-18650-protected-with-8a-pcb/

What about RGB LED for the Switch to display the current battery voltage level?
Or even an separate small two number LCD to show either percent or voltage?
https://de.aliexpress.com/item/10000-Lumen-7R8-Lantern-Lamp-Torch-7x-Cree-R8-Tatical-led-flashlight-With-LCD-Display-4x18650/32626441348.html

My suggestions for covering the USB-Port against dust and splash/crumbs:
Either an slide port cover like this kind:
https://www.delock.de/produkte/N_20652/merkmale.html

Or an removable which could be fixed with an small cord:
https://www.delock.de/produkte/S_64013/merkmale.html?setLanguage=en
https://www.delock.de/produkte/S_64015/merkmale.html?setLanguage=en

This is looking great guys. Let me put in one more vote for USB-C PD, if it’s financially viable, it would be super awesome and make this a very modern design. Plus my phone and laptop all use USB-C so it would be mighty useful for me. But if not, that’s ok.

Thanks for all the hard work, I’m so excited!

That’s not what I see from the PCB layouts posted.

Just one linear FET driver, not two, no separate connections for balancing two different colour temperature LED banks, and the layout is seriously messed up around the FET on the posted layouts (will never work). I’ve tried to reverse engineer it but the layout makes no sense, it’s all over the place and shorts itself out at several points around the FET.

Agreed, it does look like a rip-off of led4power’s design. But it makes no provision for the lowest modes, firefly, moonlight etc. which led4power does by simply driving them directly from a separate MCU pin through a high value series resistor, PWMed as necessary.

To try to do that all using just a big FET in linear mode with a (very basic, none-differential) Op-Amp for feedback is difficult enough to cover just say 8 bits=255 levels for ramping = 7 useful discrete levels.

If intending to PWM the thing for lowest modes, then e.g. the Op-Amp had better be tuned carefully with the FET and LED characteristics to have a hope of working predictably. Op-Amp selection will be critical. The characteristics of the FET and the LEDs may dominate anything beyond obtrusive visual PWM.

As will the selection for minimal standby power in e.g. E-switch applications. Micropower/minimal offset voltage/high differential gain/gain-bandwidth product, temperature stability etc. etc.

Presumably this has all been bread-boarded successfully so I needn’t worry.

I know we argue with each other a lot, but I have a lot of these same concerns.

If I understand correctly, this design has not been built or tested. It’s still pretty theoretical, so we don’t really know how well it would work. The general concept performed well in the BLF GT — a constant current circuit regulating power from 10% to 100, and below that it used PWM at 10 to make lower levels work. But I don’t think BLF has done that with a linear FET opamp before.

The first linear FET design, using attiny85, had issues with too few pins. It sacrificed control of the button LEDs, and it put the enable function for three different circuits on one pin. This basically makes the “PWM for low modes” useless at in-between tints like 3500K and 4500K, but, assuming it doesn’t break the USB circuit, it should still work at exactly 3000K, exactly 5000K, and exactly 4000K (ish). It makes some parts of the color space inaccessible. And it means the main LEDs would have to be at 10% power or higher, depending on tint choice, in order to function as a power bank.

So there’s a newer design, using attiny84. More pins should fix those two issues. However, it isn’t a supported MCU platform yet, so it adds a significant delay while I write a hardware abstraction layer and port firmware to the new MCU. And then there’s still the unknown factor of how well the linear FET opamp would work.

This project is already over 2.5 years old, and I’d like to get it to production soon. So I’m personally leaning toward using the 7135-based driver. It’s simple, its behavior is well-understood, it meets or exceeds the project’s goals, and it already “just works” today.

The dual linear-FET design with a bigger MCU is very interesting, and may forge a new path forward for BLF drivers… but I’d prefer to work on that as its own R&D project instead of adding risks and delays to this project.