[WIP] 17mm DD+single-7135 driver / single sided / Dual-PWM

So theres really no reason to buy both boards right (except for Zener option)? I can just buy multiples of this one and use it for either driver?

Less resistance in the driver just allows higher current when the cell is fresh. The heat comes from the led so more current would mean more heat not less.

Oh Boy! More heat! Bring it!

That’s what I’m always looking for, hotter, brighter, whiter… a dragon slaying cell munching annihilator of a light! :slight_smile:

My son want’s to know the difference between disintegrate and vaporize. :bigsmile:

I meant that the driver should get less hot or is that never an issue on the FET drivers? i thought it was recommended to at least use a silicon cube on them.
I know the led would get more current thats what i am hoping will happen.

Pretty much.

  • The A17DD-SO8 is easier overall to hand-build than this driver.
  • One difference that stands out to me is the way LED+ bypasses are done on both boards. This PCB should be reasonably friendly to drilling a hole between C1 and the MCU without interfering with an SOIC clip much. The A17DD-SO8 can be drilled in the center of the PCB and hopefully not interfere with an SOIC clip.
  • I don’t think that there is space for an LDO on this design, so I do not expect to produce a 17mm LDO version for momentary usage like I did for the A17DD-SO8.

I give all of that a big meh. I’ve already made it clear in the AxxDD-SO8 thread that I don’t think lowering MOSFET resistance further will result in much/any more current. I’ll be happy to eat my words, but I would recommend against getting excited. I also agree with RBD: AFAIK the MOSFET isn’t producing a significant amount of heat. It should be stone cold.

EDIT:

The silicone cube is for a linear driver’s FET, not a DD driver’s FET. FETs don’t really produce heat when they are on or off, only when they are in between on and off. The linear driver purposefully keeps the FET in this “between on and off” region in order to regulate current. Doing so produces a lot of heat, but that only applies to linear drivers.

Thanks wight for clearing up my confusion, you are correct i had confused the two.
And now i know that a DD’s FET driver is stone cold, i had thought heat could be a problem nice that it is not.

Is it possible to make a linear driver with this kind of FET and the attiny? or is that another animal altogether :slight_smile:

You’re welcome. Yes, it is possible AND yes it is another animal altogether. The driver is a WIP: A20LDX / A17LDX. The circuit / schematic has been tested and functions (to some degree or another).

Also note that led4power has built a linear driver called the LD-1 using this sort of FET and a PIC MCU rather than an ATtiny13A. All modes are constant current without PWM. Led4power’s driver is available for sale: FS: LD-1 driver (5Amp pwm-less linear)-SOLD

I'm still not used to the lack of a bypass cap at the aTtiny's power pin (from pin8 to Gnd). My designs at work could save a lot of cost and space if IC's didn't require bypass caps... But, there are a million of these drivers out there - so its hard to argue. I'll always find a way of adding these caps.

Crux

Your PCBs at work probably have a higher component count… this one uses 8 components. The whole circuit is 10 components! My (feeble) grasp of this stuff tells me that our only source of noise is the battery’s behavior under load. Note that even on a stock Nanjg-105c they do not use the normal “1uF for every IC” but rather >3uF! Apparently that’s because there’s some bulk component to this. As long as our little cap is close enough to the MCU vs the LED I suppose inductance keeps things in check. <shrug>

You can use the cap in the normal way (with positive connected between the protection diode and the MCU), but you’ve got that boost circuit problem at that point. To fix that you’d need a Zener diode pulling the boosted voltage back down on the MCU side of your bypass cap. By that time you might as well have implemented an LDO and used the output cap on that in lieu of the bypass cap.

The design does work, and it works pretty well. The efficiency is nice on the lower modes, with a nice glowing moonlight mode. I recommend running the 350mA binned 7135s if you want the lowest possible moonlight mode. In general, it seems like you can get a lower stable moonlight mode with it than you can with the 380mA binned variety.

For my design I had to swap the PWM outputs in the firmware, but it looks like you won't have to do that.

Would it be worth it to replace the diode with a p-channel FET? The package would be three leads rather than two, which would make the footprint a little bigger, but it would eliminate the voltage drop and thus allow a higher drive voltage to the main FET's gate (to get lower resistance at lower battery voltage). The voltage sense R's could be moved to the protected side without needing to factor in Vf of the diode. The benefits (if apparent) may only be 'on paper'.

Read this pdf from Texas Instruments: www.ti.com/lit/an/slva139/slva139.pdf

There are many others - search for "battery protection FET"

Edit- Of course at this point you may want to use an LDO...so many options...so little time to test them all. I am quite impressed at the way you've been able to pack all this into a 17mm single sided board. So please don't let my comments rattle you, this is great work! I've always been torn between making something rock solid for one specific application, and tweaking it to work in several applications. Consequently some of my designs keep morphing and never get done...

Don't take your eyes off the prize!

Now that you bring it up again (good time to point it out) I recall that you’ve mentioned the performance difference between the 350’s and the 380’s before. It would be neat if someone could explain why they behave that way. Anyway thanks for bringing this up.

The PWM lining up on mine was dumb luck. I was prepared to specify swapping the PWM in firmware if necessary. When laying out this design I started with the FET and moved out from there. I think this is more or less how it went, although I didn’t start saving revisions until the design was fully functional (other than vias). I try to start saving earlier but it’s hard.

  1. place FET optimally.
  2. place LED+ diagonally across from BAT-
  3. place 7135?
  4. place MCU.
  5. fill in the rest
  6. vias come last

I rotated the MCU a little bit and then shuffled the small components until it looked like I could hook things up. When I later realized that the PWM pins were correct I was delighted of course.

EDIT: added stuff I forgot to write.

In this case I think we simply don’t have the space for an inexpensive P-channel FET. Also recall that some folks are transplanting Nanjg driver components onto these, so the less extra stuff they have to purchase the better. We really haven’t done any testing to show whether the lower resistance is worthwhile once battery voltage drops. Napkin math indicates that it’s not a big deal (eg the major limitation at that point is LED Vf).

Thanks for the link, that’s a concise and to the point article. I’ll keep the P-channel FET in the back of my mind and see if I can make use of it somewhere.

RE: actually releasing things… you see my strategy, right? Who cares if it works or not, just label everything WIP! :stuck_out_tongue: I’m absolved of all blame! :wink: :wink:

Wight, I think it’s your fault AR lenses scratch easily. It’s probably even your fault that electronics stink when they burn.

We can blame you for whatever we want to. :stuck_out_tongue:

That's the spirit! :)


https://oshpark.com/shared_projects/7sNNyipn
v009 changes:

  • Changed from 18x 0.5mm GND vias to 16x 0.6mm GND vias for spacing reasons.
  • Pulled GND via circle in a lot. The entire minimum annular ring for each via is now spaced the minimum trace distance from the board edge. This should be fully compliant with OSH Park’s design rules.
  • Swapped out lame LFPAK56 outline. It was nowhere near correct and just wasting all kinds of space. I used a Power-SO8 outline that came with Eagle and filled in the blanks by hand for now. I reduced the amount of solder paste laid down under the tab vs the old outline, somewhat like what NXP actually recommends. I’ll fix a real part later.
  • Tilted the squiggly line of vias at a rakish, dashing angle more fitting with today’s styles and trends.
  • Minor silkscreen changes.

I think what’s left to do at this point is pin down a name and then clean up the sloppy silkscreen on the bottom.

Here’s a WIP screenshot from v008:

Wight, have you had a chance to play with any of the LFPAK33 FETs yet? I ordered some and have a few boards almost done with them, but haven't had a chance to try any yet. I put one on the 15mm version of this board and according to NXP it looks like they are pretty much equivalent to the LFPAK56 FETs.

Heh, frankly I haven’t thought any about them, although as you probably realize I have a couple on hand. I haven’t really shopped to see what’s available. Where it fits I feel like Power-SO8 is the ideal footprint since there are so many options available. It’s a very popular package and no one is likely to be unable to source appropriate parts.

That said, when I re-attack buck circuits I’ll be looking hard LFPAK33 and the other 3.3x3.3 MOSFETs. I can see why it’s a good choice for the 15mm layout.

I forgot to mention this: when I ran the CAM job for v009 I ran both the old and the new job and uploaded both to OSH Stencils. Sure enough, both were off. I think it’s just a flawed setup on their end.

Hmm… How about Mercutio, whose actions brought together two warring houses? Or Defarge or Manette from A Tale of Two Cities?