Well, ok, probably not quite 16, but I just realized, now that we're doing bit banging for 4-channel PWM, we can also pass in an extra "ramp" level into the interrupts with maybe 2 or 4 extra bits.
Updated to reflect further thoughts:
So the first idea is use extra bits as a prescale divider. So if you have 4 bits with a value of example 0010 (2), only process the PWM 1 out of 4 cycles. So a PWM of 100 becomes effectively 25, 100 but only 1 processed one out of 4 cycles so on 25% of the time.
This means you can get PWM of less than 1. You still have to pay the price effective PWM speed one way or another for hardware that doesn't like low PWM, either by slowing the clock or by using a lower-8-bit value of for example 4 and an upper 4 bit value of 8. Then you get blocks of 4 pulses, helping the hardware, but only process 1 out of 8. Either doing that or slowing the clock 4 times and processing PWM of 1 half the time, you're still paying that price on the PWM speed curve the same, but you can go farther down that curve than before.
An alternative way is to run it as true 12 bit, by using the high bits to determine how many full cycles to stay on for and then use the 8 bit interrupt match to stay on for the next partial cycle. That's neat because it's real 12 bit operation and programmatically simpler, but that way the pwm is _always_ slower. For 4 extra bits it's 8 times slower. Getting fast PWM at high levels and low PWM at low levels will require one of about three combinations of the tricks.
For a buck or boost (where the idea came up) controlled by a PWM to voltage filter, you might not even pay that slowdown price using the first technique, since it's not even real PWM. the issue would be if the driver can output that low. If not, 2nd channel real PWM is the solution there.
So it seemed somehow true say 10 bit should be possible, just going at it the wrong direction. Should make the extra two bits most significant bits.
So you imagine 4 pwm cycles where you turn on at the start of the first one. The extra 2 bits determine which cycle you turn off during. The standard PWM gives you the interrupt then at the right time during the cycle, so the 8 least significant bits. The key difference here is only turning on the PWM 0 match at the start of the first cycle, not every 0-match. So that's a tiny bit more code, but not much and it means you can make a true 16bit single ramp definition, making things less weird to understand.
Sounds interesting. I’m not very good at spotting tiny differences anyway, so greater resolution isn’t a goal for me right now. But I’m sure there are plenty of people who will find it very useful. And, as we continue moving toward ever more powerful emitters, the added resolution on the low end will become increasingly important for all of us, I suppose.
It's not about tiny differences. It's about getting to very low modes in single-channel drivers. 1/255 just doesn't get you to moon on a single channel (no 7135). FETS might have trouble handling this anyway, but the idea was for voltage controlled drivers where the PWM is being filtered to produce a voltage.
It's not clear the electronics involved even has the resolution needed to control things reliably at this level though. There are other ways, but they may not always be available.
It's simple. So normally PWM is done entirely in hardware. You set the clock rate, and a counter ramps and resets, and the light comes on at x and turns of at y, 32 thousand times a second but that's all handled by the chip. For PWM4 the hardware won't set the pins automatically. It will call an interrupt, and we set the pins there. So we can just only turn on one cycle out of every 4 and then you've got a PWM that's 1/4th as bright as the normally lowest one. That's the main idea. You don't get that level of control from the "automatic" pwm, or better to say you don't need it, but might as well consider the advantages it could bring.
For hardware that has trouble at low PWM, this can still work, just have to either slow the clock down for moon mode, or start with a PWM of maybe 4 and then divide it by 8. You'll still get groups of 4 clock-ticks, so the hardware works, but you'll only process one out of 8 of them. Or likewise you can have 4 times slower pulses by lowering the clock, but that still only makes PWM of 1 work well, then process half of them and get to 0.5.
In combination you can get lower moons on single channel hardware than possible before. You still have to pay the price of effectively slower PWM. That second part has always been a known tradeoff for getting to PWM of 1 on some hardware, but 0.5 or 0.25 was never possible at all. With this, it is, but the tradeoff still continues. Still have to pay the price somehow for the hardware limit.
Updated OP with improved summary of thoughts,... now with both methods.