I didn’t look much at what in available for smaller PFETs, which would be 2x2mm I suppose, but I doubt their resistance will be low enough.
Also there is enough space for a 3.3x3.3 sized one.
I just found space for 1 more additional cap for second level filtering, i’ll play and see what i get. Smaller then 3x3 Pfet will burn out. Now looked at your SiSS61DN and it looks like to burn as well. It have low safe operating area in DC mode…
I measured the voltage drop across the 2x2 PFET on the H600, 104mV at 3.4A = 31mΩ
Looking at Vishay’s offering, the DC current they can take is rather limited, arround 8A max.
Are we looking at the same DS ? The Rdson limited DC current goes up to 20A, the TPS61288 caps at 15A.
Great job thefreeman!
I´ve recently take a look to 2x2 FETs and even the better ones had too high resistance and too low ampacity.
If you want to save space, placing inductor over the rest of driver components, may be a better approach.
https://www.vishay.com/docs/75322/siss61dn.pdf page 4 last graphic . At 3-4v it can take only 800mA in DC mode?
Mounting coil on top of component is Chinese crap engineering ;))
The horizontal axis is Vds, drain source voltage, not Vgs (which is negative for a Pfet, in our case it varies from –4.2 to –2.8V), Vds is very low, Vds = Rdson x I
Thanks.
Coilcraft has a series with raised inductors but their thermals are not as good and in the end quite limited in current compared to the XAL7030 equilavalent. And if something taller is to be used, I think a XAL7070 better suited.
Quadrupel : at 15A Vds ≈ 0.075V.
Understanding MOSFET datasheets: Safe Operating Area (SOA) | Video | TI.com Watch from 13:15
Im using those
I’m used to seeing reverse polarity protection before the MCU only. I guess here it’s on the power path. Why does it have to be there as well?
See Loneoceans answer two posts after.
I see, thx Mike. 
Loneoceans post explains it well, basically it does this :
Plus probably through the logic circuits as well.
Since we need to protect the power path we need a power mosfet. High side PFET is the easy way,here the SISS61DN has max DC current of 20A and max Rdson of ~5mΩ at the voltage we’re driving it, with 15A in still means a voltage across it (Vds) of 75mV and 1.125W of power lost.
We can also use a low side NFET which have better characteristics than PFETs, but this means that the circuit GND and batt- are different, the layout is bit less simple, it’s quite practical to have a GND/batt ring around the circuit, some drivers use a NFET, I saw pics of an Armytek driver and they used one.
Or we can use a high side NFET with an ideal diode controler (a gate driver with a charge pump) but that’s more components.
It looks slightly better indeed, good find.
Those are interesting links but they don’t contradict what I said.
You seem to be confused about what Vds means since you want it at 3~4V (battery voltage ?)
The drain source voltage is the voltage across the mosfet. It is that high when the mosfet is off (very high resistance) and the rest of the circuit is at 0V. But when we drive it below Vgs=–2.8V the resistance drops very low, below 5mΩ, it’s like a resistor and the voltage across this resistor is our Vds.
If we’re drawing 10A then Vds will be 0.005 x 10 = 50mV. This is simply ohm’s law and this is what the Rdson limit line is.
At some point though we hit the thermal stability limit for DC, which for SISS61DN is 20A, same for 63DN.
What is the rest of the diagram for then ? Linear mode, that is when when have a higher Vds due to a higher Rdson.
An example is a linear led driver, when we want to drive an LED at 5A with a 3.2Vf and a battery voltage of 4.2V, then Vds = 1v (4.2-3.2V) and Rdson = 0.2Ω. In that case it would not be in the SOA of the 61DN and it would blow.
Now imagine drawing 10A with a Vds of 4V, that’s 40W in the mosftet, of course it’s going to blow!
OK… whatever( i do not understand and i wont ;)), but my choice is Pfet with higher safe operating area in DC mode .
Fasltad’s mosfet models have high resistance by default, change beta to ~90 to simulate a ~5mΩ PFET : https://tinyurl.com/yhsmyjqr
Oh yesss!
I managed to make anduril works with HDR ^:) I used the LED2_ENABLE function, normally it just mirrors LED_ENABLE. To change that I copied the code for enabling the LED channel 1 only for a portion of the ramp in fsm-ramping.c. Now I can put in cfg :
LED_ENABLE_PIN_LEVEL_MIN 1 //boost enable LED_ENABLE_PIN_LEVEL_MIN 150
LED2_ENABLE_PIN_LEVEL_MIN 18 //high range enable
LED2_ENABLE_PIN_LEVEL_MIN 150
The high range mosfet turns on level 18 (for example).
There is one issue, that I kind of knew would happen, it blinks at full power when the mosfet turns on. When we are on top of the low range, that is 1023/1023, the RC filter needs some time to settle to 1/1023( about 10ms to 90%, ~20ms to 99% with the current RC filter), so when the mosfet turns on the output is very high and falls to the expected power in ~20ms, hence the blink. Reducing the capacitor of the RC filter would help but it will only do so much since it can’t be too low for filtering the PWM signal.
For now I have added one buffer 1/1023 level before the mosfet turns on, obviously not ideal since if you stop ramping exactly on it you’ll find yourself in moonlight (0.01lm) instead of a low mode (~3lm). The actual solution would be to add a delay to the mosfet, something like 40ms should be plenty, not sure how to do that though.
But for now this a good enough solution.
I’m so happy to have it now fully working after so much time developing it :D
I received the 0.8mm PCBs, they look quite sturdy, I roughly cut a ring in a 1mm copper sheet :
With this the XAL7030 only stick out about ~1.9mm above the ring, probably low enough to fit in a D4v2, KR1, or other linear/fet lights with shallow driver cavity.
I ordered 0.8mm 2oz cooper option too. It will perfectly fit in to D10 headlamp ;))