New Driver: PD68 "DoubleDown" - 17/20/22mm FET+4

They look fine. I am hoping to get a 22 built this weekend, if time allows.

I’ve managed to build a working driver. Running bistro on it. Very very nice. Thank you Pilotdog!

Sweet!

Made some minor adjustments to bistro to best suit my likings so far and I must say: what an awesome firmware she wrote!

You did a hell of a job with that driver board as well.

This is probably a dumb question, but what is pin3 being used for these days?

On this board? Not really anything. The TripleDown uses it for an output.

All of my SOD323 diodes say 47 on the top with no line on either end. I am assuming that the 4 would be on the side away from the line drawn on the 22mm driver? The anode on the diode is to the left of the label on the diode if held in normal reading position.

Diode datasheet.

I have not built the 22mm version of this driver until now.

It is going to get Bistro on a tiny25! :slight_smile:

Thanks Matt

I used to have some diodes that said “41” and the ‘1’ was the “line side”. You can always try it, if you have it on wrong the driver simply won’t power up.

That is the direction I thought they went, thanks for the confirmation. What diodes do you use now and is there a reason other than price? That is just for reverse polarity right? It would be much easier to install them if they were 0805 rather than those darn things with legs.

yeah it’s reverse polarity. I actually really like the 323 package for those diodes.

I usually order the cheapest diodes that work for the application, and that usually means stuff that’s about to be phased out. So every time I have gone back to order more, I’ve had to find a different part number that wasn’t discontinued.

For FET drivers it’s important to stick with reasonably low Vf on the protection diode. This keeps gate voltage as high as possible.

wight, can you explain the need for the higher gate voltage? Does it matter if you aren’t PWMing the FET?

Sure. Gate voltage corresponds to RDS (ON), right? The MCU drops a lot of voltage (the ATtiny13A is spec’ed at 0.7v drop I think) on it’s own. That’s after the protection diode has dropped whatever number, maybe 0.2v. Subtract that from your battery voltage - which at high drive currents is sagging.

For an example, let’s imagine a light where the battery voltage drops to 3.7v under full load. Subtract 0.2v, then subtract whatever the MCU drops (0.7v?)… so gate voltage can be no higher than 2.8v at this point. Look that up on your RDS (ON) graph and see what’s happening… we are probably flirting with poor FET performance at that point.

I think you may be overestimating my understanding of the subject.

I understand and can follow the voltage losses going through the diode and mcu before getting to the FET gate, but I have no idea why that needs to be above a certain level or what “RDS” is.

From reading discussions previously I somehow came to the assumption that that only mattered if we are PWMing the FET. Are you saying it always matters?

Yes, it always matters. Take a look at Figure 8 on Page 7 of the PSMN3R0-30YLD datasheet. Another “telling” place to look is Figure 10 on the next page.

A minute or two looking back and forth between those graphs and the back-of-the-napkin math will likely get your mental cogs turning! :GRADE:

EDIT: RDS is the “Drain-Source” resistance, it’s very important for our applications. It must be kept as low as possible in a DD driver.

So let’s see if I understand this (in extremely simpleton terms). I had assumed that applying voltage to the gate pin on the FET just served as a notification to the FET like, “Hey, FET! Open the door!”.

But really, the voltage on the gate is what is actually “opening the door”? So if the voltage is too low on the gate, it will take longer to “open the door” and it might not be able to “hold the door” all the way open, causing extra resistance?

edit: BTW the graph was helpful. I never realized how close we were operating to the cliff on these voltages

Is Rfet needed here? If so, what is the suggested value?

Thanks Matt

I thought it would be. We are that close to the cliff!!

You are correct, the voltage is “holding the door open”. We never get the door 100% open (zero resistance), but we can achieve very low resistances. As has been pointed out to me in the past: at low battery voltages the resistance becomes a moot point because we don’t have enough voltage to drive the LED hard anyway. Ideally I’d like to see decently high drive currents through 50% to 75% of a battery if possible. I’ll certainly take whatever I can get, but a lot of that depends on the LED Vf in most cases. At a higher drive current the problem is exacerbated. I’m not sure how that fits in to the “door” analogy, but it doesn’t really need to - you get the idea.

Eyeballing that “knee” in the graph is one of the things which motivated me when moving the battery voltage divider. Measuring “before” the protection diode means that we can put in whatever diode makes sense without having it drastically affect voltage monitoring.

Your assumption is a common one. I have made the same assumption in the past. An FET seems a lot like a solid state “relay” but it’s really not very similar at all. What a letdown, right? Carefully looking over those graphs is what makes DD FET selection take forever.

Home work: OK, I kept this one in reserve. It’s an easy assignment, don’t worry. Now that you’ve achieved a handle on this concept… go lookup the same graph in the SiR800DP datasheet.

Well that explains why some people love it. Still not sure if I’ll jump to using it though, it’s a whole $1 more! :smiley:

Thanks for the education. :GRADE:

a $1 more? Where? Not from Richard: $0.80 —> $1.35, or am I missing something?