The 3.3v variant probably isn't a good idea for an FET since we want a higher voltage at the gate to minimize on resistance. If the attiny is only being fed 3.3v, it can only output at most 3.3v; 3.3v will turn the FET on, but it may not be fully on. I would go with the 5V variant, given the choice.
Doh! What he said.
DBCstm, that should be just fine. To elaborate: 3.0v is the lowest voltage LDO I think should be used with PSMN3R0-30YLD and the majority of other inexpensive low-Rds(on) + high current FETs. Any lower than that and the MCU cannot provide a high enough Vgs to the FET to guarantee low resistance [low Rds(on)] at high currents. Some of the FETs in the $2 range like the SiR800DP and PSMNOR9-30YLD [which RBD recently pointed out in the A17DD-SO8 thread] could handle an even lower Vgs if you needed them to.