Buck driver design advice needed

stevetto · 2019-03-25T17:57:30.000Z

Lexel:

Our calculations are quite similar.

stevetto · 2019-03-25T19:33:56.000Z

I have modified my schematics based on your suggestions. Thanks for that.

A made a low-pass filter for the LDO, separated the GND for the high and low current parts of the driver and also made a low-pass filter for the pwm signal of the mcu and connected the Iadj pin to the filtered pwm signal through a voltage divider.

I used this tool to determine the RC values. R=4,7k and C=1uF will result 0.026V ripple and 0.01s settling time.

http://sim.okawa-denshi.jp/en/PWMtool.php

Does this design looks reasonable?

Lexel · 2019-03-25T20:17:35.000Z

the position of I adjt capacitor is not right, it should be between ground and the chips pin, or add a 2. there for 2 stage low pass
also the resistors seem odd 4.7k upper voltage divider then a 2. divider 30 and 10k

original GT driver uses upper voltage divider 10k then lower 3.3k in parallel with 1uF

R5 10k useless?

clientequator · 2019-03-25T20:26:14.000Z

i love to see so many new design coming up! Keep it up the good work!

kikkoman · 2019-03-25T20:27:45.000Z

But now you’ve left the EN pin unused… with I_adj dimming alone, you won’t reliably get below a certain threshold (10% or so). Too high for moonlight mode, hysteresis issues etc. To get below that, you combine PWM dimming (EN line) and analog dimming (I_adj).
You go down to the lowest stable analog value, from there on down it’s PWM.
Here’s the ramp values from Anduril on the GT driver for example - PWM1 is EN, PWM2 is I_adj:

// First 60 values: level_calc.py 1 60 7135 4 5.0 255
// Remainder: all 255 (buck driver at 100% duty cycle)
#define PWM1_LEVELS 4,5,6,6,7,8,9,11,12,13,15,16,18,19,21,23,25,27,30,32,34,37,40,43,46,49,52,55,59,63,66,70,75,79,83,88,93,98,103,108,114,119,125,131,137,144,150,157,164,171,179,186,194,202,210,219,228,236,246,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255

// First 60 values: all 25 (buck driver at 10% power)
// Remainder: values 61-150 of level_calc.py 1 150 7135 1 3 3000
#define PWM2_LEVELS 25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,26,27,28,29,30,31,32,33,35,36,37,38,40,41,42,44,45,47,48,50,51,53,54,56,58,59,61,63,65,67,69,70,72,74,76,79,81,83,85,87,89,92,94,96,99,101,104,106,109,112,114,117,120,123,125,128,131,134,137,140,143,147,150,153,156,160,163,167,170,174,177,181,184,188,192,196,200,204,208,212,216,220,224,228,233,237,241,246,250,255

P1 and P2 go to the switch, correct? I think the convention is to pull the switch line low (with internal pullups enabled). For flexibility in terms of firmware, I’d do the same too.
You can also use higher values for the voltage divider if you want to minimize parasitic drain.

The ride never ends

stevetto · 2019-03-25T20:28:58.000Z

Lexel:

??? the position of I adjt capacitor is not right, it should be between ground and the chips pin, or add a 2. there for 2 stage low pass also the resistors seem odd 4.7k upper voltage divider then a 2. divider 30 and 10k original GT driver uses upper voltage divider 10k then lower 3.3k in parallel with 1uF R5 10k useless?

R5 wanted to be a pull-down resistor for the pwm pin of Attiny I just posted an old image by mistake.

Rfltr=4.7k and Cfrtl=1uF are the low pass filter and the output of this filter is diveded by a 10k and 3,3k resistor that I also corrected and connected to Iadj.

Cfltr is connected between the pwm pin and the GND. I have 2 GND traces (high and low current) joined at battery minus.

The idea was to filter the 5v pwm and than divide it.

Isn't is correct? Did I misunderstand something?

Lexel · 2019-03-25T20:34:26.000Z

5V*(3.3k)/(4.7+10+3.3k)=0.91V on I adj.

also EN pin should be on 2. MCU channel for Moon PWM dimming

stevetto · 2019-03-25T20:51:59.000Z

I do not need lower modes than 25% pwm.
But why not, I will try to do this dual EN-Iadj settings. Lets go…
P1 and P2 go to a piezo switch. I will test it how it behaves in pull down way. But I do not want to use any of the popular firmwares, they contains much more features and a “complicated” UI I do not need.
I only need and off and a few (ex. 25, 50, 100%) on states. That’s all.

kikkoman:

But now you’ve left the EN pin unused… with I_adj dimming alone, you won’t reliably get below a certain threshold (10% or so). Too high for moonlight mode, hysteresis issues etc. To get below that, you combine PWM dimming (EN line) and analog dimming (I_adj).
You go down to the lowest stable analog value, from there on down it’s PWM.
Here’s the ramp values from Anduril on the GT driver for example - PWM1 is EN, PWM2 is I_adj:

// First 60 values: level_calc.py 1 60 7135 4 5.0 255
// Remainder: all 255 (buck driver at 100% duty cycle)
#define PWM1_LEVELS 4,5,6,6,7,8,9,11,12,13,15,16,18,19,21,23,25,27,30,32,34,37,40,43,46,49,52,55,59,63,66,70,75,79,83,88,93,98,103,108,114,119,125,131,137,144,150,157,164,171,179,186,194,202,210,219,228,236,246,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255

// First 60 values: all 25 (buck driver at 10% power)
// Remainder: values 61-150 of level_calc.py 1 150 7135 1 3 3000
#define PWM2_LEVELS 25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,26,27,28,29,30,31,32,33,35,36,37,38,40,41,42,44,45,47,48,50,51,53,54,56,58,59,61,63,65,67,69,70,72,74,76,79,81,83,85,87,89,92,94,96,99,101,104,106,109,112,114,117,120,123,125,128,131,134,137,140,143,147,150,153,156,160,163,167,170,174,177,181,184,188,192,196,200,204,208,212,216,220,224,228,233,237,241,246,250,255

P1 and P2 go to the switch, correct? I think the convention is to pull the switch line low (with internal pullups enabled). For flexibility in terms of firmware, I’d do the same too.
You can also use higher values for the voltage divider if you want to minimize parasitic drain.

The ride never ends

Lexel · 2019-03-25T20:57:51.000Z

stevetto:

I do not need lower modes than 25% pwm.
But why not, I will try to do this dual EN-Iadj settings. Lets go…
P1 and P2 go to a piezo switch. I will test it how it behaves in pull down way. But I do not want to use any of the popular firmwares, they contains much more features and a “complicated” UI I do not need.
I only need and off and a few (ex. 25, 50, 100%) on states. That’s all.

kikkoman:

But now you’ve left the EN pin unused… with I_adj dimming alone, you won’t reliably get below a certain threshold (10% or so). Too high for moonlight mode, hysteresis issues etc. To get below that, you combine PWM dimming (EN line) and analog dimming (I_adj).
You go down to the lowest stable analog value, from there on down it’s PWM.
Here’s the ramp values from Anduril on the GT driver for example - PWM1 is EN, PWM2 is I_adj:

// First 60 values: level_calc.py 1 60 7135 4 5.0 255
// Remainder: all 255 (buck driver at 100% duty cycle)
#define PWM1_LEVELS 4,5,6,6,7,8,9,11,12,13,15,16,18,19,21,23,25,27,30,32,34,37,40,43,46,49,52,55,59,63,66,70,75,79,83,88,93,98,103,108,114,119,125,131,137,144,150,157,164,171,179,186,194,202,210,219,228,236,246,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255,255

// First 60 values: all 25 (buck driver at 10% power)
// Remainder: values 61-150 of level_calc.py 1 150 7135 1 3 3000
#define PWM2_LEVELS 25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,25,26,27,28,29,30,31,32,33,35,36,37,38,40,41,42,44,45,47,48,50,51,53,54,56,58,59,61,63,65,67,69,70,72,74,76,79,81,83,85,87,89,92,94,96,99,101,104,106,109,112,114,117,120,123,125,128,131,134,137,140,143,147,150,153,156,160,163,167,170,174,177,181,184,188,192,196,200,204,208,212,216,220,224,228,233,237,241,246,250,255

P1 and P2 go to the switch, correct? I think the convention is to pull the switch line low (with internal pullups enabled). For flexibility in terms of firmware, I’d do the same too.
You can also use higher values for the voltage divider if you want to minimize parasitic drain.

The ride never ends

yes but humans eyes are not linear 25% brightness needs only 6.25% light,
10% 1%

kikkoman · 2019-03-25T21:11:27.000Z

Hmmm the first filter was "more correct" but you have to take the 4k7 into account. So R7 would have to be more like 25k. But you can simplify the thing:

P1 and P2 go to a piezo switch. I will test it how it behaves in pull down way

Ah I see. Is it one of those integrated things that need their own supply? Because those I think exist in several variants like open-drain, open-source (or pnp, npn) etc. that dictate how you have to interface them.

OK apparently that's not the case.

stevetto · 2019-03-25T21:32:16.000Z

kikkoman:

Hmmm the first filter was "more correct" but you have to take the 4k7 into account. So R7 would have to be more like 25k. But you can simplify the thing:

P1 and P2 go to a piezo switch. I will test it how it behaves in pull down way

Ah I see. Is it one of those integrated things that need their own supply? Because those I think exist in several variants like open-drain, open-source (or pnp, npn) etc. that dictate how you have to interface them.

OK apparently that's not the case.

Ok. and I can save some space.

stevetto · 2019-03-26T18:17:42.000Z

Is there any more remark, suggestion regarding to this design?
Otherwise I will start wotking on the pcb.

Thank you in advance.

stevetto · 2019-04-08T18:32:34.000Z

I have replaced the FET and the Schottky diode to the same as used on the GT driver.

And have just finished the pcb design. The high and low current part is separeted to the top and bottom side of the pcb.

The bottom side is quite dense, but the pcb is only 26mm.

kikkoman · 2019-04-08T19:08:43.000Z

No objections so far but these few:
Clearance from components to copper areas looks way too low. (This makes it quite hard to tell what’s going on there.) Those from traces to copper look about right. You should check these values against the PCB manufacturer’s guidelines anyway before submitting.
There’s still a few copper islands that could be removed (e.g. under L1) , and conversely, a few pads could have more copper around them. (B- and L- on the FET side look funny)

And are you sure the LM3409 has a good GND connection? It looks kind of boxed in, and I don’t see any vias to the GND plane on the other side. Can’t hurt (for thermals too!)
edit: the ATTiny GND looks like it goes nowhere too…

stevetto · 2019-04-08T20:00:43.000Z

kikkoman:

No objections so far but these few: Clearance from components to copper areas looks way too low. (This makes it quite hard to tell what’s going on there.) Those from traces to copper look about right. You should check these values against the PCB manufacturer’s guidelines anyway before submitting. There’s still a few copper islands that could be removed (e.g. under L1) , and conversely, a few pads could have more copper around them. (B- and L- on the FET side look funny) And are you sure the LM3409 has a good GND connection? It looks kind of boxed in, and I don’t see any vias to the GND plane on the other side. Can’t hurt (for thermals too!) edit: the ATTiny GND looks like it goes nowhere too…

Thank you. I have increased the clearance to 0.5mm between parts and traces to solid regions. I use easyeda to design and I also order the pcb from them. They offer : min. trace 3.5 mil min. space 3.5 mil Unfortunately I can’t remove islands separately in easyeda, I can remove all or keep all. Or I do not know how to do it. I think LM3409 and attiny GNDs are connected. B- and L- looks strange because I used separate GND for the high and low current side and this is the place where these grounds are joined.

kikkoman · 2019-04-09T10:37:18.000Z

stevetto:

Unfortunately I can’t remove islands separately in easyeda, I can remove all or keep all. Or I do not know how to do it.

Yup, I can’t find that either. Though personally, I’d remove them all and patch up where necessary. (i.e. a GND ring on each side, build up the areas I want with polygons)

I think LM3409 and attiny GNDs are connected. B- and L- looks strange because I used separate GND for the high and low current side and this is the place where these grounds are joined.

OK I can see it now. But now you’ve isolated the FET side outer copper pour from GND entirely , you could easily use that and stitch it with a copious amount of vias to the other side. I also think you could put the central GND point opposite right under (or beside) the LM3409, use both planes (remember the 3409 needs heatsinking too), and you could save yourself a lot of convoluted routing. As long as you avoid thin loops it’s okay.
The way it is now, you have those 2 GND connections snaking around the board forever before they reach the node.

Most important issue last, didn’t spot this before, this need to be fixed first: your input caps belong before the sense resistors, you have them after. I wouldn’t take the chance that this works without regulation issues.
On the topic of resistors: there’s 21, 21.5 and 22 mOhm resistors so you could save some real estate there.

Lexel · 2019-04-09T20:38:28.000Z

strange design
did you consider that the LM3409 also produces some heat?
it has for a reason the colling pad this should contain 4 vias and be thermally bounded to ground on bot sides and this ground should also be connected to drivers rim, you insulated it all the way around

I would put it way closer to the boards edge

also your board has no spring pad, usually this also helps with bypassed spring to absorb some heat from the driver

go with all resistors and the small “no power” caps to 0603 size

use a TO277B diode to save some space

do not insulate battery ground from diver edge ground!

you also have your inductor and switching MOSFET on pretty few copper, no viases to get some heat moved to the other side
same with the reverse diode, for god sake connect that ground there to driver rim for heat sinking, especially with significant higher input voltage than LED there is a lot heat produced by this diode

Lexel · 2019-04-09T22:45:40.000Z

I just made a quick design on 26mm with your via power connection

as you can see there are way more efficient variants to trace such a driver, not your spagetti tracing

tried here to explan the wiring and heatflow

of course there is more potential to get the heat paths better

I looked at your design and direct copper heat transfer is very small

stevetto · 2019-04-10T11:44:00.000Z

Thank you very much for the remarks. I will try to redesign my pcb.
But I have a question again.
I was suggested to separate the GND of the high and low current part of the driver.
My idea was to put all high current parts on side of the driver and low current part on the other and finally I joined the GNDs only at the minus battery terminal.
If I use so many vias on the pcb everywhere I will join the GNDs at several locations earlier and not just at the final step.
In this case does it have any sense to separate them?

stevetto · 2019-04-10T19:01:15.000Z

Modified again: