No objections so far but these few:
Clearance from components to copper areas looks way too low. (This makes it quite hard to tell what’s going on there.) Those from traces to copper look about right. You should check these values against the PCB manufacturer’s guidelines anyway before submitting.
There’s still a few copper islands that could be removed (e.g. under L1) , and conversely, a few pads could have more copper around them. (B- and L- on the FET side look funny)

And are you sure the LM3409 has a good GND connection? It looks kind of boxed in, and I don’t see any vias to the GND plane on the other side. Can’t hurt (for thermals too!)
edit: the ATTiny GND looks like it goes nowhere too…