Ah, that explains why he talks about being able to dissipate 15W if you use a seperate FET board.

My deepest dive into circuit design, not being an electrical engineer, involved accidentally dissipating too much power in a FET, due to not having a pull-down resistor to drain the gate voltage while PWM’ing it - the FET was spending some time every cycle with its gate voltage in an intermediate, partial on state. I burned up several FETs this way before a tech helped me figure it out.

My experience makes suspicious of that approach, but I could see it work if there is an appropriate amount of cooling.