This is the stock 105C on the ‘wooden light’ above. It has eight 7135s and drives a mystery bin XML2.
I set up the PWM to 9.4 kHz phase-correct. (Actual frequency is 7.2 kHz, due to the un-calibrated clock we get at 4.8 MHz).
Since we are running at 7.2 kHz, each of the 255 sub-periods of the PWM signal is around 0.55 us (1/7200/255).
This is with a PWM duty cycle of 32/255:
We are zoomed in on only one ‘on’ pulse of the PWM train.
The yellow trace is the control pin on the MCU.
The cyan trace is the ‘output’ pin of the 7135s going to the LED.
Both are referenced to ground (normally cell negative terminal, although I was using a bench power supply).
The horizontal scale is 2 us per division.
The vertical scale is as indicated on the screen capture, but is not very important. Basically the 7135s are fully on when the blue trace bottoms out and fully off when at the other end. (I did trace the current as well, but the signal is much more noisy, using a 4” piece of AWG 22 as shunt does not help.)
So we see on the yellow trend that the MCU output turns on at the 2nd division from the left, struggles for 2 us, then settles as a straight line at 4 V.
The 7135s output oscillates for another 4 us (there is a control loop in each chip, and this wave is probably created by the feedback loop trying to catch up with 350 mA set-point). So our theoretical 32/255 x 2.8 A becomes more like 22/255 x 2.8 A.
This what we get at 2/255 PWM:
and 4/255:
8/255:
No surprises, we are just cutting the trend we see on the first screen capture.
Finally around 10/255 we start to get to the stable output level, just before the end of the pulse:
So basically we have a 6 us unstable transition period before the 7135s get to do what they are supposed to.
Typical circuit design strategy would limit this unstable operation to less than 10% of total operation to get acceptable stability, linearity, efficiency, repeatability, etc. That means not using pulses shorter than 60 us.
That is around 43% PWM at 7.2 kHz. And 86% PWM when using fast PWM at 13.5 kHz!
So we see we are not really playing inside the ballpark.
It also unfortunately translates to an ideal PWM frequency of 1/(60 us x 255) = 65 Hz.
Not going to happen.
So we have to live with the inconsistent PWM results or find a better way of doing it.
My compromise for the moment is to lower the PWM to 2.2 kHz.
Also lowering the self-imposed 10x criteria above to 2x limits me to using pulses longer than 12 us.
At 2.2 kHz, each 1/255 sub-period is 1.8 us. So PWM duty cycles greater than 7/255 is ‘stable’.
2.2 kHz PWM, 8/255 duty-cycle, more than half the ‘on pulse’ gives stable current: