One VERY annoying habit of Eagle when manually routing traces is it’s idea of where you want to do the trace. A lot of times it won’t allow you to start a trace where you want to. It wants the trace to start at the nearest point to an airwire when you do/update the ratsnest display. I often have to rip up an existing trace to get it to allow me to put in the trace where I want it to go.
You managed to drop vias and route traces on this version… Do it the same way 
(Green circles = Via), (Blue Lines = Bottom Side Trace)
Ok, I think I got it. Gerbers to come soon. :D
Well, it routed…
1 ) Some of your traces route too close to other ‘things’. You must maintain AT LEAST 6 mills (and better 8 or 10) of clearance between a ‘thing’ (via, trace, pad) on one net and a ‘thing’ on another.
2 ) there is no need for the three vias on the trace right next to your connection hole. That’s a thru-hole wire pad, so you can just connect directly to it on the bottom side of the board - you don’t need to via back up to the top side before making the connection. Then you can also eliminate the single via next to the bottom-center SOT-89. Just run that trace directly from the Wire-Hole to the group of four vias in the center on the bottom side.
1. Is there a way to have eagle fix that automatically do you know? (More a question for Texas than for you)
2. Fixed it. :)
Ok, so here it is. I looked through it and I believe I fixed all of the spacing errors.
Can you post the .BRD file? I don’t have my Gerber viewer handy.
Fatten up all the vertical etches to the 7135’s. At least to the power pins.
And I’d scootch E8/E7 and E23/E24 over a smidge from the edges of the board.
Also clean up the ziggy routing on those etches around the edge of the board.
Do you want that blue etch around the edge of the board? You should do a board outline on the DIMENSION layer.
You’ve still got multiple locations with gaps smaller than 0.006”
Delete the fifth via in this group. It’s physically on top of the two outside ones and will break-out when drilled.
Not critical, but traces like this are really bad practice. It will ‘work’ fine, but its good to get in the habit of not doing stuff like this.
You might want to re-size or re-position the Silk-Screen text. This is what will actually be printed when they clear for solder-mask openings.
You have solder-mask openings around each of your vias. I would remove the solder-mask opening from top and bottom side. The copper in these areas will be exposed if you leave these mask openings here.
PPtk
I’d leave the via openings in. That way you can fill the vias with solder and get better current carrying capacity.
Ok, did all that.
http://dl.dropbox.com/u/84514277/1amc7135per1mmdiameter.brd
Edit: This is a response to post # 49.
Tex, They’re all on the VDD pins. 200uA per part typical current. If it were me, I’d take 3 of the four of them out of each set…
I don’t see any changes… is that the correct link/brd file?
Ahhh yes, a single via and thin etch is fine on the control signals. Only the power handling signals need to be beefy.
@PPTK, fixed everything except for the silkscreen labels and the soldermask openings. Updated files to come.
.brd file still seems to be the same old thing…
Maybe I screwed up the link? Here it is re-uploaded.