Those are the only three interfaces and once dealing with those three things, the internals don't know any different. Forget the gate driver. That was an early idea. They won't work well, or not those anyway. You just need a small pfet to drive the nfet. But yeah the one "internal" thing is if it handles voltage sensing at low bias offsets well. That's not entirely clear. I might buy one and try to test. It's not simple. Need a scope, and well, maybe need to build a buck, probably not though, just a scope and some RC. I'll stare at their pseudo circuit more.
Ok, so the other thing is switching delay, but the IC needs some accomodation for this anyway, and as I've read in detail how this works, I'm very convinced that's fine. As switching delay gets too long you'll get a minimum duty cycle at high frequency since it will take time for the on cycle to shut off, which raises the voltage minimum. 10% would be doing really bad (100ns delay at 1Mhz) and that's a 1.7V increase, and even then you can just cut back the frequency to reduce that for 1S drivers.
The thing that's big is that current sensing n-fet, but it's probably not too big.
EDIT: now I almost forgot what one of those drivers does. One of them actually can drive an n-channel mosfet on the high side, generating the extra voltage needed to drive it. That actually is cool because it doesn't require flipping the buck and might even get around worries about the sense resistor, but I think I decided that one was too large and a bit slow. I'll have to look again. I kind of like flipping the buck better if it will work.