Single CAP PWM slow DAC: V, ripple, offset, etc, calculation reference

I posted this idea here in the context of analog buck control:

But I thought the details of this DAC are a little more general and worth their own post. This isn't novel, and Ti has documents even describing multi-cap setups to reduce ripple farther for instance, but maybe it's useful.

I'd post a typeset document but BLF doesn't keep images around so this is better.

We want to charge cap to a DC voltage from a PWM. You construct a voltage divider connecting the PWM output to the top of the cap through R1, and the top of the cap to ground through R2. The bottom of the cap connects directly to ground. Presumably something else connects to the top of the cap to sense its voltage.

In the special case of the LM3409 IC current adjust pin that inspired this, there is also an approximately 5uA current passing directly to the cap from the IC (used to bias an internal diode). I'll call this bias current I_B. In general this could be positive or negative or other more resistive leaks may exist that can be folded into R2 instead.


C: capacitance

I_B bias current onto cap from LM3409 (or such). Use 0 for other applications.

D: Duty cycle of PWM

V_i: Input voltage from PWM (output voltage of mcu)

V: voltage on output cap, our analog output signal.

G: voltage divider "gain" factor: R2/(R1+R2)

To find the equilibrium voltage you just write down the average current for one full PWM cycle (on-time current current times D plus off-time current * (1-D)) as a function of V_i and V. Then set it equal to zero and solve for V. The result is:

Output voltage

V=GDV_i + G R1 I_B

Neglecting I_B it's just the obvious input voltage times divider times duty cycle. Great.

Ripple, peak to peak:

To get ripple you just write down (either) the on time (or off time) current and multiply by D (or 1-D) and /fC.

The result in terms of V is:

V_pp= [ V/(R1G)-I_B](1-D)/(fC)

Fractional ripple is then

V_pp/V= [1/(R1G)-I_B/V](1-D)/(fC) and the I_B term should normally be small/neglectable

This is a maximum as duty cycle approaches zero (zero output voltage). It increases with decreasing G (as max output voltage is set lower max ripple gets worse) BUT i'ts always zero at D=1, ie at max output. For this reason it's still best to use the divider, not softare PWM, to set the max output, because then at max output control ripple is zero, and that's where it matters most.

Neglecting I_B, a simple estimate of max factional ripple is obviously:

V_pp/V= 1/(R1*C*f*G)

Response time, tau, or effective RC:


(easily seen by writing down dV/dt=I_average/C, using the same average I as above, and simply examining the coefficient on the V term)

It can be tempting to make R1C huge to avoid ripple and/or to create nice soft 1/2 second transitions. But other currents, leakage etc must be considered, in this case I_B. See the V offset note below. However C can be made large without negative consequences, if you can fit a large enough capacitor in.

V offset/minimum:

In the output voltage equation above notice the offset voltage I_B*R1*G creates a minimum output voltage and an offset to the voltage curve. High values of R increase this. For the LM3409 application this will mean the highest modes saturate the input and moonlight won't be reachable (but we'll use other tricks for that anyway).

The offset as a fraction of max output voltage is clearly:

V_offset/V_max= I_B*R1/(V_i+I_B*R1)

which if kept reasonably small is approximated by the nearly intuitive expression:

V_offset/V ~ I_B/ (V_i/R1)

So in simple terms V_i/R1 should be kept much larger (100 times if you want to reach 1% output) than the bias current.

(minor clarity edits)

In the case of the LM3409 using a singe 10uF cap and 10K R1 setup for 5 V PWM and 1.24V max output (max allowable) we can get a 2% 0.2 max ripple (at near zero volts out), 0 ripple at max out, and about 1% offset.

edited: Allowing 2% ripple actually can bring firefly down to 0.1% of total power.

I don’t have the time to dig into the details but looks good at a glance!

Thanks again, Flintrock, for all your contributions! We’re very fortunate to have you around!

Just amusing myslef. For fun, I applied it to frequency control on the LM3409. I worked out the algebra for

R1 R2

MCU-PWM ------^^^^------------ ^^^^ ------------------------ LM3904 C_off input

| |

__ ___

C_buf __ ___ C_off

| |


The LM3409 discarges Coff when the fet is on and senses it while the fet is off. Once it rises above 1.24 V, the fet turns back on. It's a clock to control the off-time. Current sense controls on time. This circuit allows software buck frequency control.

It's a bit messier math that the iadj with many more variables, so not as simple to algebraically optimize, just have to build a calculator and try some things, so I did.

If I reduce the C_off cap to 220pf from 470pf (manual has no clear spec for this, only one example, but this should be fine)

I can get about 5x range of software frequency control (so 200khz to 1Mhz for example) with about 2.5% Coff jitter. That translates to buck current jitter :(.

That's assuming 5V Vcc. Using a tiny transitor and battery voltage would imporve it all. Using a smaller C_off yet would improve it more. Using one more cap and resistor should probably improve it. I can get more control range already, but at cost of more jitter.

Not sure it's good enough to be worth it. A board could be built with jumpers to charge Coff this way or the normal way, but I placed this here, because it's exploratory.

I'll do the first simple proof:

I_avg= D(Vi-V)/R1 {on-time term} -(1-D)* V/R1 {off time term} - V/R2 +I_B {full time term} and the magic is how that re-arranges to just:

DVi/R1 - V/(R1*G) +I_B

That immediately gives the first result. The rest is rinse and repeat. Not really complex, but if nothing else I post it here for myself to find again.

My Wife is an electrical engineer. She worked for Applied Materials as process engineer and technical sales manager. Her office had a floor to ceiling, wall to wall white board. They were developing etch processes for Infineon Semiconductor one day when I walked in. The entire white board was covered with what looked like hieroglyphics to me.

LOL, I know the feeling. Like I have said, I have a firm electronics 101 understanding. The above equations are something that I have to actually sit down and really work out to understand. I can do it but it takes about 10X longer then someone with a real understanding of what is going on.

The biggest problem is the definitions of a lot of the abbreviations, takes me a lot of time to look them up and figure out exactly what is going where and doing what.

Which is why I much prefer to leave this kind of thing to those that enjoy it/understand it more then I do.

Actually, the resulting buck current ripple should be only half the off-time jitter. So that's getting to be close to 1% level, cut the cap in half again and double the resistors (that would be 1.6K each) and it's about 0.6%

Just updating this for the record, I did find a 220uF 6.3V 1206 cap (and there's a 4V 0805 for a heafty price) that should make soft transition (long RC times) work, and the Texas buck now has the footprints to find out.