I recommend considering this FET+1 driver instead of the one discussed in this thread.
This driver functions fine, but requires many important firmware and flashing considerations. All versions of the driver in this thread requires extra special firmwares, NOT a plain version of STAR or a DrJones firmware. The original version and most other versions of the driver in this thread area also one-time-flash drivers for most users: without high-voltage programming equipment it's not possible to reflash them! Reading through the thread should answer any questions you have relating to this subject.
OK guys, here's a good reason to curse my name. I present... a driver which you cannot physically assemble and which has no firmware available:
This is a combination 6*7135 and FET driver. On top you have the ATtiny13A, all support components, and the FET. On the bottom you have 7135 chips.
This driver will accept either an LFPAK56 FET or a DPAK (TO-252) FET.
I used Eagle's normal [giant] 0805 pads, so there is actually a lot more space than there looks like. A 0805 resistor is less than 2/3 as long as the overall length of the pads. Much closer to 1/2 the length actually.
I just couldn't quite squeeze in a Zener diode. I did leave enough space to replace D1 with a resistor, so stacking the Zener diode on C1 is still possible I guess.
The voltage divider for LVP bypasses D1, so new values are required. Stock Nanjg 105c values will not give correct results for low voltage protection.
I maintained 0.5mm of keepout around the edges on both sides of the board.
This driver will require a special firmware.It uses 4 pins on the ATtiny13A to control these things separately:
A. 1*7135 B. 2*7135
C. 3*7135
D. the FET
This driver will be very difficult to assemble.
The way I imagine the [non-existent] firmware to generate modes is like so:
Moonlight (unregulated w/ PWM on FET)
1*7135
2*7135
3*7135
3+1*7135
3+2*7135
3+2+1*7135 (6 total)
Turbo (FET 100% duty cycle [wide open])
Shoutout to Chloe for her post #14 in this thread explaining how to set images to 100% in the Advanced Post Editor.
You certainly know how to attract flies modders. I like this idea, the benefits of regulated output plus the overdrive of FET DD. Now you just need some programmer honey.
Texaspyro will frag your A$$ for running the signal trace under the AMC chips. Is it possible to shrink the center pad to allow the trace to run inside the chips?
Not if you want to solder a spring to it…it looks like a full 5mm pad that has some solder stop over it…any smaller and good luck even soldering a flipped over spring to it, 5mm is teeny tiny
Why? As far as I can see they both fit, it just looks unattractive. This way nobody gets caught with a board/FET pair that don’t work together and has to wait weeks for Oshpark to send a new board.
The pour is 6mm, the exposed contact is 5mm.
It uses 4 output pins for that. PB1 is PWM, that is hooked up to the FET. I should swap PB0 and PB4 so that the single 1*7135 is also on a PWM pin (PB0).
It works the other way too. I figure it’s easier to solder a 0603 on a 0805 pad than the other way around. Soldering 0805 on a 0603 is a minor pain in my butt. Thoughts?
When the time comes I want 8k or more. 8k will hold a bootloader for programming without ICSP. You should be able to program a chip which has a bootloader using 3 wires or less. Header time! Unfortunately the ATtiny85 is probably the best candidate for that and in SOIC it’s only available in 208mil package, not the 150mil we use now. It won’t fit on boards like this one. The MLF package (20M1) is an option, but you can’t bring vias up under it and pass them over to pins like I did on this board. Also realistically it’s reflow only.
Good suggestion. I was being lazy because I do not enjoy working on parts. I should make a new part that eliminates that pin and the stop. That will make it much easier to route in a semi-attractive manner. The trace still may end up under the pin. As long as you don’t have much chance of exposed copper (like a tented via that gets solder down inside it) I think it’s OK to route the trace under there.
Might help the - via by putting some top copper at angles to the FET pad just to smooth out the bump so to speak, and provide a little more copper for current flow
I can see advantages to both ideas. You have a point about versatility with the current superimposed FET layouts wight but an lfpak56 only design would give the board a bunch of extra space on the mcu side. I love a challenge so bring it on.
I took RBD’s suggestion and deleted the middle pin on the 7135’s. (and I cleaned up the traces on the bottom) Remember, the pins are still there just with no exposed copper under them.
WarHawk-AVG - I doubt that current handling will change but I will add copper around the via as an aesthetic touch.
I moved the solo 7135 onto PB0. The firmware should be able to put PWM on either the FET or the single 7135. With a single 7135 you can probably get moonlight low enough and still be regulated… I’m too lazy to try it.
It seems almost certain that a driver with one chip with a low pwm input will be capable of a lower moon mode than a driver with 8 chips at the same value. This made me think of WarHawks test board for 7135’s. By hooking that board up to a driver set to moon mode it should be possible to test various 7135’s to sort them by their low level output. They’re fixed and pretty uniform at full but not nearly as uniform at low levels. Now I have to find that thread again. Where is it? I saw it under the chair a minute ago.
Your wish is my command. For this driver and others that use multiple output pins I was thinking of using arrays for mode storage. Maybe a 2-dimensional array could hold all the modes and all the PWM settings at the same time. I think that might eat up a lot of memory though, I haven’t tried it.
